The deposition of layer sequences for III/V opto/electronic devices, such as multi junction solar cells and light-emitting diodes (LEDs), on group IV substrates is known. The electronic and optical properties of such devices are being studied extensively and the correlation between these properties and the characteristics of the substrate-epilayer interface is receiving great attention. The reason for the attention given to the substrate-epilayer interface is that, for the most part, the performance of these devices is determined by the quality of this interface.
When depositing a III/V material, for example GaAs, epitaxially on a group IV substrate, for example a Ge substrate, the formation of the atomic layer sequence of the group III and group V layers is not readily established. That is, the group IV sites (e.g., Ge atoms) can bond either group III or group V atoms. In practice, some areas of the group IV substrate will bond group III atoms and some other areas will bond group V atoms. As such, there are boundary regions between these different growth areas that can give rise to considerable structural defects, such as, for example, anti-phase domains, dislocations, etc, which adversely affect the performance of the device.
To curtail some of these undesired events, the group IV substrates are usually vicinal substrates with an off-cut angle ranging from 0-15°, or any other suitable angle. These vicinal substrates offer terraces and step edges where ad-atoms, that is, atoms arriving at the growth surface, can attach with different bond configurations. That is, various surface reconstructions can occur, e.g., 2×4, 2×2, 4×2, etc., thus providing greater order in the growth process. Some of these surface reconstructions are better adapted to be As-stabilized (arsenic-stabilized) and, as such, surface reconstruction can be an important factor in the III-V growth. Therefore, the off-cut angle, the surface reconstructions, and the growth parameters can affect the semiconductor epitaxy and the layers can have different ways of growing based on that, and on the strain in the epitaxial layers compared to the substrate depending on the relative size of their lattice constants. For example the step-flow growth, the layer-by-layer growth, and the 3D-growth have been observed to occur depending on the conditions as described for example in Lippmaa et al in Applied Physics Letters 76, 2439 (2000) or in other semiconductor growth references. In the Step-flow growth the off-cut (or miscuts) gives rise to atomic steps on the surface. In step-flow growth, atoms land on the surface and diffuse to a step edge before they nucleate a surface island. The growing surface can then be viewed as steps traveling across the surface. This growth mode is typically obtained by deposition on a relatively high off-cut substrate, or depositing at elevated temperatures. In the layer-by-layer growth, islands nucleate on the surface until a critical island density is reached. As more material is added, the islands continue to grow until the islands begin to coalesce into each other. Once coalescence is reached, the surface typically has a large density of pits. When additional material is added to the surface the atoms diffuse into these pits to complete the layer. This process repeats itself for each subsequent layer. The 3D growth is similar to the layer-by-layer growth, except that once an island is formed an additional island will nucleate on top of the first island. Therefore the growth does not persist in a layer by layer fashion, and the surface roughens each time material is added.
In devices such as, for example, solar cells having III/V compounds epitaxially deposited on a group IV substrate, it is often desirable to create part of the device itself in the group IV substrate by diffusing, for example, a group V species in the group IV substrate. As an example, for solar cells, if a group V element is diffused in a p-type Ge substrate, an n-type region is formed, giving rise to a p-n junction. This p-n junction becomes photo-active and can be part of a single or multijunction solar cell. However, when depositing the III/V compound at typical process temperatures (500-750° C.) on the Ge substrate, the group V element of the compound tends to diffuse, with little control, in the substrate thereby making the formation of a predictable p-n junction difficult. In cases involving group IV substrates with a pre-existing p-n junction, as could be the case in the hetero-integration of III-V opto/electronics on Ge, SiGe and SiC electronic circuits, the deposition of an overlaying III/V compound can modify the doping profile of the pre-existing p-n junction resulting in subpar performance of the p-n junction and device. Consequently, the electrical characteristics are not easily controllable. In such situations, it can become quite difficult, if not impossible, to attain and maintain the desired doping profile and the electrical characteristics of the substrate's p-n junction, such electrical characteristics including, in the case of solar cells, the open circuit voltage (Voc).
Furthermore, when depositing the III-V layers, the group IV atoms will diffuse from the substrate into the epitaxially deposited III/V layers. Hence, layers within the initial 0.5-1 μm of the III/V layer sequence can be highly doped with the group IV element when the excessive diffusion of group IV atoms is not curtailed through the use of suitable nucleation conditions and materials. Group IV atoms like Si and Ge are, at moderate concentrations, typically n-type dopants in III/V semiconductor materials. However, due to their amphoteric nature (i.e., the fact that they can generally act as n-type or p-type dopants at large concentrations in III/V semiconductor materials) these atoms can cause a large degree of compensation (combined incorporation of n- and p-type impurities) when incorporated at concentrations much larger than 2×1018 cm−3, often leading to a strong deterioration of electrical and optical properties of the host semiconductor layer.
U.S. Pat. No. 6,380,601 B1 to Ermer et al., hereinafter referred to as Ermer, teaches deposition of GaInP on an n-doped interface layer formed on a p-type Ge substrate, and subsequent deposition of a GaAs binary compound on the GaInP layer. The phosphorous of the GaInP layer tends to not diffuse in the Ge substrate as deeply as the arsenic of a GaAs layer would. Thus, the phosphorous doping and subsequent deposition of the GaInP layer allows better control of the doping profile of the n-type layer of the Ge substrate and consequently, leads to a better control of the electrical characteristics of the p-n junction formed in the Ge substrate. However, the problem with having a GaInP interfacial layer at the Ge substrate interface is that the morphology of devices prepared under typical epitaxial process conditions for these materials is not ideal: defects often abound. As defects generally act as recombination sites for electrical charge carriers (electrons and holes), the performance of such devices is generally not good as the number of defects is high. It would appear that extreme nucleation conditions (temperature, deposition rate, group V overpressure) of the Ermer GaInP interfacial layer are required in order to obtain devices with suitable morphology.
Improvements in III/V devices and structures formed on group IV substrates are therefore desirable.